The complex problem of analyzing and understanding the dynamic behavior of computer systems is aided by the use of data collected by performance monitoring hardware associated with the system processor. Unfortunately, thorough analysis requires monitoring coverage of such a vast breadth of processor states that hardware support is unrealistic. Moreover, as computer designs increase in complexity, their dynamic behavior becomes less intuitive, causing computer designers to rely more heavily on empirical data to analyze system behavior and to provide a basis for making hardware and software design decisions.
In the past, most of the processor states that are useful for performing system analyses have been accessible to external instrumentation because of the implementation technology. At low levels of integration, most machine state, bus transactions and other signals were visible on the module interconnect, edge connectors and backplanes. Thus, data could be easily captured and post-processed for use in system analysis.
As more and more logic is integrated onto VLSI chips, many relevant system events are no longer accessible by external instrumentation. Chip designers have attacked this problem by including hardware structures such as multiplexors and counters within chip designs to collect information about process states. But the full function and flexibility of measurement previously available with external instrumentation cannot be implemented on the VLSI chip because of design constraints. Typically, the scope of performance monitoring hardware is limited to tracking a few hard-wired internal events. While the data collected by such hardware is valuable for systems analysis, there is no flexibility in scope, triggering mechanism or means to change the representation of output data. Accordingly, an improved system and method for evaluating the performance of computer systems that allows flexible empirical measurement of process states without adversely impacting system performance are desirable.